This invention relates to a logic circuit, and more particularly to the testability of a programmable logic array.
In the design of logic circuits, programmable logic arrays (PLA) have become increasingly more important for designing combinational logic circuits. These programmable logic arrays offer a greater variety and flexibility in logic design while lowering parts count and inventory requirements, and are also proving to be very cost effective. With programmable logic devices, a designer can customize a reliable, high volume integrated circuit to fit a specific application, and quickly.
However, until recently, little has been done to test the programmable logic array in the unprogrammed state. This is due in part to the unavailability of an adequate number of test points on the chip. The various testing techniques devised require augmenting the PLA with a substantially large amount of additional logic which can interfere with the normal operation of the PLA logic or which requires and dissipates additional power even while the PLA is operating normally.
The present invention presents a novel approach for providing test capability of a programmable logic array in the unprogrammed state with some small amount of added logic which is inoperative and dissipates no added power while the PLA is operating in its normal environment.